1. Field of the Invention
An embodiment of the present invention relates to microelectronic device fabrication. In particular, an embodiment of the present invention relates to a noble metal alloyed with a barrier material as a single alloyed underlayer that functions as both a barrier layer and a seed layer for metal contacts.
2. State of the Art
The microelectronic device industry continues to see tremendous advances in technologies that permit increased integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second), to be packaged in relatively small, air-cooled microelectronic device packages. These transistors are generally connected to one another or to devices external to the microelectronic device by conductive traces and contacts through which electronic signals are sent and/or received.
One process used to form contacts is known as a “damascene process”. In a typical damascene process, a photoresist material is patterned on a first surface of a dielectric material. The dielectric material is then etched through the photoresist material patterning to form a hole or trench extending at least partially into the dielectric material from the dielectric material first surface. The photoresist material is then removed (typically by an oxygen plasma) and a barrier layer may be deposited (such as by atomic layer deposition or physical vapor deposition) to line the hole or trench in order to prevent conductive material (particularly copper and copper-containing alloys), which will be subsequent be deposited into the opening, from migrating into dielectric material. The migration of the conductive material can adversely affect the quality of microelectronic device, such as leakage current and reliability circuit reliability.
After the formation of the barrier layer, a seed material is deposited (such as by physical vapor deposition) on the barrier layer. The seed material provides a nucleation site for a subsequent plating process, for example, performing a conventional copper electroplating process to form a copper layer. The resulting structure is planarized, usually by a technique called chemical mechanical polish (CMP), which removes the conductive material and barrier layer that is not within the hole from the surface of the dielectric material, to form a conductive via (if a hole is filled) or a trace (if a trench is filled), as will be understood to those skilled in the art.
Barrier layers used for copper-containing conductive materials are usually nitrogen-containing metals, including, but not limited to tantalum nitride, tantalum carbon nitride, titanium nitride, and titanium carbon nitride. One issue is that the noble metals used a seed layers can have poor adhesion to such barrier layers when the two are deposited as distinct layers, particularly when under vacuum. Due to this poor adhesion, the noble metal seed layer tends to dewet (agglomerate) during thermal annealing in latter processes. This can lead to poor electromigration performance and may generate voids during copper plating, if the noble seed layer becomes discontinuous, as will be understood by those skilled in the art. If fact, delamination may occur during the CMP process, if the adhesion is poor enough.
Therefore, it would be advantageous to develop apparatus and techniques to overcome the limitations of such barrier layers and seed layers.